A Hyperconcentrator Switch for Routing Bit-Serial Messages

In highly parallel message routing networks, it is sometimes desirable to concentrate relatively few messages on many wires onto fewer wires. We have designed a VLSI chip for this purpose which is capable of concentrating bit-serial messages quickly. This hyperconcentrator switch has a regular layout using ratioed nMOS and takes advantage of the relatively fast performance of large fan-in NOR gates in this technology. A signal incurs exactly 2 lg n gate delays through the switch, where n is the number of inputs to the circuit. The architecture generalizes to domino CMOS and BiCMOS as well. The hyperconcentrator design has applications other than message concentration. It can be used in a superconcentrator switch to provide fault tolerance when interconnections are nonfunctional. Multiple hyperconcentrator switches can be conngured into a large partial concentrator switch. The hyperconcentrator design can also be used in a processor datapath to allow various manipulations on bits, including barrel shifting, APL-style compression and expansion, and bit interleaving. + = = log typeset in Roman _ appears in two diierent sizes within the text ^ A i line over A does not extend out over subscript O italic uppercase \oh" o italic lowercase \oh" uppercase Greek letter theta lowercase Greek letter phi uppercase Greek letter omega lowercase Greek letter alpha lowercase Greek letter beta lowercase Greek letter mu lowercase Greek letter epsilon